For example, the inventors examined the following technologies associated with a method for inspecting fine patterns formed on a semiconductor substrate.
In accordance with a recent tendency toward fine semiconductor device structures, careful consideration is being given to distribution of essential pattern sizes due to the presence of edge roughness, i.e., unevenness along edges of a fine pattern formed on a semiconductor substrate. The line width of a transistor's gate pattern is equivalent to a gate length that determines device characteristics. A fine process of 100 nm or less causes the roughness of approximately 5 to 10 nm based on 3σ (σ: standard deviation) for a line on the pattern side. If this roughness is converted into 3σ for the line width, i.e., the gate length, a distribution of 7 to 14 nm results. The roughness may become 10% or more of the gate length. Very locally, though, there may occur a portion where the gate length becomes approximately 10% shorter.
The distribution of gate lengths in one gate region may degrade the transistor performance such as an increased leak current in the power-off state, a threshold voltage shift, and the like. Especially when the gate length becomes 80 nm or less, the threshold voltage largely depends on the gate length. The management of line width variations is therefore important.
Firstly, it is necessary to measure the edge roughness and line width variations using an appropriate method. The appropriate method here includes providing fully accurate measurement in accordance with the gate width, i.e., the line length of a transistor to be evaluated and estimating a deviation from the true value. This is because the roughness measurement provides different results depending on measurement area sizes and measurement intervals. The prior art has not taken this point into consideration and determined measurement parameters in reliance on measurer's experience. Accordingly, variations are found in measurement results for the same pattern.
Secondly, it is necessary to quantitatively estimate the transistor performance degradation caused by a line width variation and keep track of a margin for the line width variation.
The relationship between a gate length and a threshold voltage is described in non-patent documents 1, IEDM Technical Digest, December 2000, pp563–567 and 2, 2002 Symposium on VLSI Technology Digest of Technical Papers 15-3, 2002.
For example, non-patent document 3, Digest of International Conference on Simulation of Semiconductor Process and Devices (SISPAD), 2000, pp. 131–134, reports a methodology for calculating performance degradation of a transistor caused by edge roughness in a gate pattern. In this document, a calculation flow is described assuming that the line-width distribution in one gate pattern has been already obtained.
Nevertheless, it has been difficult to obtain the real line-width distribution in a gate pattern accurately thus far for lack of the function in SEM. Thus, transistor performance has been estimated only from the standard deviation (sigma) of the line-width distribution. For example, non-patent documents 4, Proceedings of SPIE, 2002, Vol. 4689, pp. 733–741 and 5, IEEE Electron Device Letters, 2001, Vol. 22, pp. 287–289 report this study.
The former example calculates the transistor performance by varying actual gate lengths σ, 1.5σ, and 2σ smaller than the designed value and alerts possible performance degradation.
The latter example uses a gate-length fluctuation, value ΔL, to divide the gate into two portions in which one causes an actual gate length to be smaller than the designed value and the other causes an actual gate length to be greater than the designed value. The gate length variation for each portion is set to ±ΔL which is input to an equation for finding a threshold voltage from the gate length, thus finding a threshold voltage variation.
On the other hand, when a single line contains a plurality of transistors having short gate widths, a long-period fluctuation in the line width causes a variation in the average gate length for each transistor, namely an average of gate lengths along the gate width direction for individual transistors. Accordingly, a variation occurs in the transistor characteristics. This phenomenon is described in non-patent document 6, Japanese Journal of Applied Physics Part 1, 2000, Vol. 39, pp. 6792–6795. for example. The gate length fluctuation is not the only cause of a variation in the transistor performance. As finer devices are available, however, an effect of the gate length fluctuation becomes not negligible. In this manner, a small-period fluctuation degrades the device performance. A large-period fluctuation causes a variation in the device performance. It is necessary to develop a technology that accurately measures a line width variation using an appropriate technique and clarifies an effect thereof on devices.
The above-mentioned method estimates electrical characteristics of devices on the semiconductor substrate by finding a gate width fluctuation from the pattern shape. Further, there is another method of finding a gate width fluctuation from a contrast of the image using a scanning electron microscope (hereafter referred to as SEM). The use of this method can detect continuity or discontinuity of devices without calculating gate shapes in detail. This is described in patent document 1, JP-A No. 159616/2001 for example.
The experiments of analyzing roughness shapes are described in patent documents 2, JP-A No. 349002/2000 and 3, JP-A No. 243428/2002, for example. These methods calculate similar roughness shapes using a spatial-frequency distribution of data obtained from actual line pattern images or extract contribution of specific frequency components from the original data.